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Honored Contributor
Honored ContributorPessimistic Timing Analysis
Hi I have a design running on Cyclone III. My design is constrained and it works on physical hardware; but there are some errors in the output data processed and generated by FPGA. SO we have a wo...
Altera_ForumHonored Contributor
Honored ContributorHello msj,
You should have a correctly constrained design and you have to check all timing models from TimeQuest (ex. Slow 85C, Slow 0C, Fast 85C, Fast 0C, etc..) to see if they meet your requirements. Where have you bought chip?
