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rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Peloader hang in clock calibration

Hello, The following function get hang in my application. I can't knows exactly why, because preloader is getting compiled with debug information (Is there a way to Turn it off)? What I see is: ...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello Sir,

May I know how did you build your preloader? is it through bsp-editor?

Furthermore, which device is that?

Thank you

  • rshal2's avatar
    rshal2
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi,

    We are using bsp-editor, with device ASXFB5 (arria V) with quartus 15.1.

    I suspect that it is related to clock input clock1 ? but since debugging behaves a little tricky (I tried to remove some parts, but it behaves in-consistently), therefore I think it would be better if I build with no optimization.

    Yet, It always hang cm_basic_init() routine.

    I verified the following:

    osc1 and osc2 are 50M with scope.

    bootinfo register is 0x2b5 (bsel=0x5, csel=0x2).

    What can be the reason for preloader hang in cm_basic_init?

    Thanks

    • rshal2's avatar
      rshal2
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      In further debugging it seems it get hangs right here:

      	/* Take all three PLLs out of bypass when safe mode is cleared. */
	DEBUG_MEMORY
	cm_write_bypass(
		CLKMGR_BYPASS_PERPLLSRC_SET(
		CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_EOSC1) |
		CLKMGR_BYPASS_SDRPLLSRC_SET(
		CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_EOSC1) |
		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENUM_DISABLE) |
		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENUM_DISABLE) |
		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENUM_DISABLE));

      for some reason, I can't put a breakpoint in this line but if I remove the above line from code, then I get into next line and continue debugging.

      Any idea what it means ?

      Thanks!

  • rshal2's avatar
    rshal2
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hello,

    These are the next steps I've tried:

    1. change csel from 0x10 to 0x0. Now it behaves slightly different. I manage to pass the previous problematic code line, but in just the next line of code it get hangs:
    /* clear safe mode */
	DEBUG_MEMORY
	cm_write_ctrl(
		readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_CTRL_ADDRESS) |
			CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));

    Why should it hang here ?

    2. I than tried to skip "cm_basic_init" routine.

    Now I manage to continue till the end of preloader before jumping to u-boot.

    What does it mean ? Why cm_basic_init fails to configure pll ?

    3. I've also noticed the following patch:

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06202014_496.html

    Should this patch be applied with quartus 15.1 ?

    Note: I try to debug preloader using debugger. Is this the reason for the pll calibration issue ?

    Thanks

  • rshal2's avatar
    rshal2
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi,

    I suspect that it is issues of osc1 reference clock.

    In our case it is 50Mhz, and csel is 0.

    Maybe the actual accuracy of our clock is not sufficient ? I haven't find the precision requirement for osc1 in reference.

    I also see that it terrasic DE-10 they use 25Mhz as input with csel=0, maybe 50Mhz is too much near the limitation of csel=0 (10 to 50Mhz) ?

    Thanks