Forum Discussion
AnuragSH
New Contributor
New ContributorPDN Tool - What is core clock frequency
I am using Stratix 10 device and wanted to know what exactly the "Core Clock Frequncy" refers to in the PDN 2.0.?
Is it the Core power supply regulator switching frequency or the FPGA Core referen...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
The Current Ramp Up Period parameter allows you to specify the number of clock
cycles consumed by the pipeline. You can select a Long, Medium, Short, or Custom
setting.
The pipeline registers in the design impact the power drawn. Refer section 1.2.2.1.6 of the user guide for its description: https://www.intel.com/content/www/us/en/docs/programmable/683293/current/rail-group-summary-section.html
Regards
