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Altera_Forum
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11 years ago

PCML and LVDS clocks, and fitter placement error

I inherited code for high-speed serial data transfer on the Terasic Cyclone V GX dev board. The 1 Gbps link is done with a GXB_RX block (Cyclone V Transceiver Native PHY IP), and the rx_cdr_refclk p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks for the good suggestion. I was worried about using two different clocks, but I didn't know about the xcvr internal clock network. I've verified that the code compiles when I use X3 on either HSMC port A or B.