PCML and LVDS clocks, and fitter placement error

If you are using xcvrs across both, it is possible to use just on of the reference clocks (probably X3 as the other one may be useful later on in the project) and then distribute that across both of the transceiver banks using the transceiver internal clock network which should be inferred automatically by clocking a transceiver on one bank with the reference clock of another. Otherwise you will end up with two not necessarily synchronous clocks (e.g. X3 might be 125.00001MHz and X4 could be 124.999999MHz) which could lead to issues.