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Altera_Forum's avatar
Altera_Forum
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10 years ago

PCML and LVDS clocks, and fitter placement error

I inherited code for high-speed serial data transfer on the Terasic Cyclone V GX dev board. The 1 Gbps link is done with a GXB_RX block (Cyclone V Transceiver Native PHY IP), and the rx_cdr_refclk p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

For Stratix V's (not sure about Cyclone V's), the only way to use an LVDS clock to drive the transceivers is for it to be one of the dedicated clock inputs that can drive the Fractional PLL Strip on the in the same corner that the transceiver is in.

The other option is you drive the clock into one of the GX Transceivers and configure the design to use that as the dedicated clock, but to do that you need to drive the clock into either RX1 or RX4 in a transceiver bank (again based on knowledge of Stratix V, not Cyclone V).