PCIe/DDR Timing

Hello,

I created two projects one that implements the PCIe core and one that implements the DDR2 HP core. The PCIe project also handles DMA and basically just consumes the data during the DMA read and makes up data during a DMA write. The DDR2 project adds fifos in front of the DDR core to handle commands and data.

Both of these projects compile and work fine alone with no timing violations. However, when I plug in the code from the ddr project into the pcie project so that the DMA actually reads/writes data from/to the ddr, I get a timing violation from the pcie pll output clock with a slack of ~ -.2ns and a tns of ~ -2ns.

My first question is whether this is caused by the fitter routing some clocks to slower paths. If this is the case, how could I specify better routing to those clocks?

I am still at the learning point where fixing timing issues is intimidating. Previously, I fixed my timing issues by making sure I am not demanding too much from a certain FPGA speed category. In this case, the 2 projects fit and work correcly on the same FPGA.

All help is really appreciated! I can provide any info if needed.

Using Arria GX -6