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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

PCIe reference clock requirement while programing the fpga.

Hi we are using stx10 1SM21BHU2F53E2VG and 1SG10MHN3F74C2LG at both there is PCIe IP altera_xcvr_native_s10_htile we encounter an error while programing the fpga , if the 100Mhz reference...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi

Thanks for your permission to close this case.

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel