Forum Discussion

OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

PCIe reference clock requirement while programing the fpga.

Hi we are using stx10 1SM21BHU2F53E2VG and 1SG10MHN3F74C2LG at both there is PCIe IP altera_xcvr_native_s10_htile we encounter an error while programing the fpga , if the 100Mhz reference...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I wish to follow up with you about this case.

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel


OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi ,

I'm trying to collect more data and snapshoot to in order to provide more details about the issue .

the issue is complex to explain -

in general , the once the REF clock of the PCIe is not working , the programing/burning the fpga and the of the PCIe Serdes (the Phy) is not done .

if it is better to close this issue , and later on I will open new one , or this one , it is ok from my side.

thanks

Or.