Forum Discussion

OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

PCIe reference clock requirement while programing the fpga.

Hi we are using stx10 1SM21BHU2F53E2VG and 1SG10MHN3F74C2LG at both there is PCIe IP altera_xcvr_native_s10_htile we encounter an error while programing the fpga , if the 100Mhz reference...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel


  • OrF's avatar
    OrF
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    this is not answer my question , I was taking about the stage of programing the fpga not on the stage of activating the PCIe with the host.

    I will bring more accurate snapshoot about the error .

    Or.

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,

      Appreciate if you can provide me any error code so that we can look deeper on that.

      Regards,
      Wincent_Intel