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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

PCIe reference clock requirement while programing the fpga.

Hi we are using stx10 1SM21BHU2F53E2VG and 1SG10MHN3F74C2LG at both there is PCIe IP altera_xcvr_native_s10_htile we encounter an error while programing the fpga , if the 100Mhz reference...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Do you mean to connect the refclk pin to internal FPGA generated clock? The input reference clock, refclk, must be stable and free-running at device powerup for a successful device configuration.


Regards,

Wincent_Intel