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Has anyone tried interfacing the PCIe master logic to a dedicated dual ported memory block?
So you'd tell the logic the address in the dual ported memory, the PCIe address (64bit),
the transfer length (maybe limited to a single TLP), and the direction and then read a status
bit for completion.
This ought to be simpler (and use a lot less resources) than the schemes that need a DMA engine with an internal fifo large enough for the PCIe data bursts.
The transfers themselves would be scheduled by other logic (eg a nios cpu) which could an fpga-side data copy for data that doesn't permanently reside in the correct memory block.
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Hi Dave, I have been somewhat busy and had used dual ported IMEM with one port for NIOS and one port for the PCIe Bar master ... but you are indication the PCIe master port ... that would fetch
from the dual ported memory and send out as a TLP ... Can you say how you configure the PCIe core to do that ( master / DMA function ). ?
Also, for Avalon MM interconnect, can you answer this , to get a greater than single DW write transaction on PCIe , is that a reflection that the Avalon MM transaction was also a greater than DW transaction.
ie 64 bit transaction or a burst 32 bit transaction ?
One final question while I am here ... I have only used the PCIe Hard IP in Cyclone, Arria and Stratix FPGA's .... I want to know how to control two TLP level items.
1) the Relaxed Ordering ( RO ) bit .
2) the AT bits that will define a normal address 2b00 versus a ATS translation request or a Read or Write with a cached ATS translated address.
I have a feeling these may require the Soft PCIe IP which is licensed .
Thanks, Bob.
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