Pcie link training failed (CycloneIVGX)

Hi all!

I have problem with link training between FPGA(CYIVGX) and DSP.

DSP: Ltssm alredy located at state 0x00 and 0x01 (detect.quiet and detect.active).

FPGA: Ltssm alredy located at state 0x03 (polling.compliance).

I do not understand what is the reason of my problem.

I'm used megafunction IP Compiler for PCIe (without QSYS) and ALTGX_RECONFIG.

http://www.alteraforum.com/forum/attachment.php?attachmentid=12739&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12740&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12741&stc=1