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Altera_Forum
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14 years ago

PCIe Legacy Interrupt Handling

Hi ,

We are using CYCLONE IV GX PCIe core (Native endpoint Mode) in our FPGA based card which is plugged on windows XP based system. We are unable to handle legacy interrupt for the same .Also I would like to add that we are using jungo win driver to develop driver for the card. Is there any specific procedure and handshaking required to handle the legacy interrupt. We have following observations

· Some time application ISR is called twice for single interrupt

· After servicing interrupt for 10-20 times it gets stuck and we are not able to get further interrupts

As per Jungo Windriver document, PCI card has to provide Interrupt Command Status register for kernel to clear the asserted interrupt which we are unable to figure out from ALTERA documents.

Thanks,

Chandra

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hi,

    I also face the same problem. Did you get it already?

    Any advice relating toi PCIe Interrupt Handling would be welcome.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Hi ,

    We are using CYCLONE IV GX PCIe core (Native endpoint Mode) in our FPGA based card which is plugged on windows XP based system. We are unable to handle legacy interrupt for the same .Also I would like to add that we are using jungo win driver to develop driver for the card. Is there any specific procedure and handshaking required to handle the legacy interrupt. We have following observations

    · Some time application ISR is called twice for single interrupt

    · After servicing interrupt for 10-20 times it gets stuck and we are not able to get further interrupts

    As per Jungo Windriver document, PCI card has to provide Interrupt Command Status register for kernel to clear the asserted interrupt which we are unable to figure out from ALTERA documents.

    Thanks,

    Chandra

    --- Quote End ---

    What version of Quartus are you using?

    From memory.....

    V11.0 QSYS had a problem where spurious pcie int messages were sent (or not sent) which affected interrupt operation. This sounds like what you're seeing.

    V11.1 QSYS had a problem with gaps in data DMA'd to host memory.

    V12.0 QSYS had a problem whith the Qsys component editor which meant you couldn't edit existing components.

    V12.1 looks like it's working OK so far.

    Nial.
  • Altera_Forum's avatar
    Altera_Forum
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    I am using 12.0 sp 2. Maybe I should install 12.1 to be sure..

    Thank you Nial.