New Contributor
ContributorHie,
You will need to connect the Reconfiguration Controller although you are not using any reconfiguration fitter. The reason for this is the CDR and Rx buffer calibration IP is dependent on Reconfiguration Controller. Hence, without the calibration IP, the performance of CDR and other PCIe circutir like SD (Signal detect) is not optimized. You could observe high CE or nCE across PVT.
Regards,
Nathan
New ContributorHI Nathan,
Pcie link of Cyclone V Fpga is connected to CPU on the board. There is no connector. FPGA is used in EP mode and pcie link serves as memory mapped Register Interface. ie the Pcie link is always on, unless the board is rebooted. What exactly is being done by Calibration IP? And does that mean that something needs to be programmed to calibration IP ? I am not clear why I need to connect the Reconfiguration controller in my case. Please elaborate ,that will be help me.
Regards
New ContributorHI Nathan,
I connected the Reconfiguration Controller to the Pcie IP. Reconfig Controller was generated with 2 Reconfiguration Interfaces in Generation Option. But I still get the same Critical warning message. Can you please help me on this.
I am using Pcie Hard IP in Gen1x1 mode. reconfig_to_xcvr[91:0] and reconfig_from xcvr[139:0] signals in the HARD IP are connected to Reconfig controller. I am not using mgmt INterface, so tied the reconfig_mgmt_read = 1'b0 and reconfig_mgmt_write = 1'b0 . clk and rst are connected and other ports of Reconfig controller are NC.
Regards
