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kgupt8's avatar
kgupt8
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6 years ago

Pcie Hard IP in Cyclone V CGXFC5C6 with out Reconfiguration controller.

I am using Cyclone V CGXFC5C6 FPGA. Using Pcie Hard IP @gen1 rate in design. Since I donot require Reconfiguration so I have not instantiated Reconfiguration Controller and reconfig ports in Hard IP are tied to 'h0. This design works without any issue on Board. But i get critical warning Message

Critical Warning (184043): Fitter was unable to find Transceiver Reconfiguration Controllers associated with the following 1 transceiver PHY IP component blocks

Is this warning really critical in my design usage?

Please help..

Regards

Kaps

4 Replies

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    6 years ago

    Hie,

    You will need to connect the Reconfiguration Controller although you are not using any reconfiguration fitter. The reason for this is the CDR and Rx buffer calibration IP is dependent on Reconfiguration Controller. Hence, without the calibration IP, the performance of CDR and other PCIe circutir like SD (Signal detect) is not optimized. You could observe high CE or nCE across PVT.

    Regards,

    Nathan

    • kgupt8's avatar
      kgupt8
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      6 years ago

      HI Nathan,

      Pcie link of Cyclone V Fpga is connected to CPU on the board. There is no connector. FPGA is used in EP mode and pcie link serves as memory mapped Register Interface. ie the Pcie link is always on, unless the board is rebooted. What exactly is being done by Calibration IP? And does that mean that something needs to be programmed to calibration IP ? I am not clear why I need to connect the Reconfiguration controller in my case. Please elaborate ,that will be help me.

      Regards

      • kgupt8's avatar
        kgupt8
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        6 years ago

        HI Nathan,

        I connected the Reconfiguration Controller to the Pcie IP. Reconfig Controller was generated with 2 Reconfiguration Interfaces in Generation Option. But I still get the same Critical warning message. Can you please help me on this.

        I am using Pcie Hard IP in Gen1x1 mode. reconfig_to_xcvr[91:0] and reconfig_from xcvr[139:0] signals in the HARD IP are connected to Reconfig controller. I am not using mgmt INterface, so tied the reconfig_mgmt_read = 1'b0 and reconfig_mgmt_write = 1'b0 . clk and rst are connected and other ports of Reconfig controller are NC.

        Regards

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    6 years ago

    Hie

    Please check my answers to your questions:

    1. What exactly is being done by Calibration IP? The calibration IP for Cyclone V (if using Gen1) is only referring to the offset cancellation of the CDR. Offset cancellation's functionality and importance is described in Pg 7-2 of Cyclone V handbook.

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf

    2. And does that mean that something needs to be programmed to calibration IP ?

    No additional programming is required. The Transceiver Reconfiguration Controller needs to be connected and supplied the correct clock frequency and the reset needs to be released.

    Per your latest note, it seems your Hard IP is connected to Reconfiguration Controller correctly. As long as reconfig_to_gxb and reconfig_from_gxb is connected, Quartus should not issue a fitter critical warning. Please attach the design achieve (.qar) so, I can analyze the error.

    Regards,

    Nathan