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kgupt8's avatar
kgupt8
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6 years ago

Pcie Hard IP in Cyclone V CGXFC5C6 with out Reconfiguration controller.

I am using Cyclone V CGXFC5C6 FPGA. Using Pcie Hard IP @gen1 rate in design. Since I donot require Reconfiguration so I have not instantiated Reconfiguration Controller and reconfig ports in Hard IP ...
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago

Hie

Please check my answers to your questions:

1. What exactly is being done by Calibration IP? The calibration IP for Cyclone V (if using Gen1) is only referring to the offset cancellation of the CDR. Offset cancellation's functionality and importance is described in Pg 7-2 of Cyclone V handbook.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf

2. And does that mean that something needs to be programmed to calibration IP ?

No additional programming is required. The Transceiver Reconfiguration Controller needs to be connected and supplied the correct clock frequency and the reset needs to be released.

Per your latest note, it seems your Hard IP is connected to Reconfiguration Controller correctly. As long as reconfig_to_gxb and reconfig_from_gxb is connected, Quartus should not issue a fitter critical warning. Please attach the design achieve (.qar) so, I can analyze the error.

Regards,

Nathan

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