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Altera_Forum
Honored Contributor
Honored ContributorPCIe Hard IP build error
i add two PCIe hard IP in my project(the FPGA device support two PCIe core),but Quartus show the error as follow, i am new to FPGA,could anybody help me solve the problem ? thanks very much! -...
Altera_ForumHonored Contributor
Honored ContributorAnd what about all the other pins? If you have two Hard-IP cores, you will have at least 4 transceiver assignments, plus clock pin assignments, etc.
