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Avi_V_888's avatar
Avi_V_888
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4 years ago

PCIe gen 4-6 lanes Agilex: maximum number of clks ready signal disabled

Hi, I using PCIe gen 4 (16 lanes) (512bit/500MHz clk , payload size:256B) CORE, in Agilex device: AGFB014R24A2E2VR0. Tests performed found that the maximum number of clks that "ready" sig...
Avi_V_888's avatar
Avi_V_888
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4 years ago

Hi Harris,

The source that feeds the PCIe core in data (and from there the core transfers it to the PC) works in real time mode.
Therefore TX flow control interface will not help here.
The problem will be solved if it will be possible to configure the core so that the ready signal will not be '0' for such a long time continuously.

Avi

Harris's avatar
Harris
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4 years ago

Hi Avi,

Unfortunately, there is no configuration for the core for this behavior. Thanks.

BR/Harris

  • Avi_V_888's avatar
    Avi_V_888
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    4 years ago

    Ok

    Thanks