Hello to all. I would need a text on the fundamentals of the PCIe. I would like to study the concepts of Endpoint, Root, and Protocol. I'm using the example hip_cvgt_g2_x4_avmm_dma128_1602.qar, downloaded from the altera's site, but I do not understand what should I change in order to read and write on the PCIe my custom data (from other logic FPGA). Can you help me? Regards, Luca

This book was very useful for me: https://www.mindshare.com/learn/pci_express/books

--- Quote Start --- This book was very useful for me: https://www.mindshare.com/learn/pci_express/books --- Quote End --- Hi Tricky! can you tell me if in a configuration consisting of : Computer (linux) -> PCIe connector-> C5GTdevboard, the read and write commands are made only from the Computer? The PCIe is similar to a master slave configuration?

Its been a long time since I worked with PCIe (and I didnt do it in much depth). But yes, iirc, the PC shouldnt receive commands from the dev board, but the dev board does need to respond appropriately to any reads etc.

PCIe is not master/slave. As long as the system is set up correctly the endpoint can master the bus and read/write the PC's memory space, such as main memory.

--- Quote Start --- PCIe is not master/slave. As long as the system is set up correctly the endpoint can master the bus and read/write the PC's memory space, such as main memory. --- Quote End --- I thought that was the case - but I only used it in a simple set up with the dev card only acting as a slave - as a port to a dual port ram between PC and another processor. What was difficult was having only an avalon streaming port as the stand alone hard core (not using Qsys) would only provide a streaming output. Here I had to write logic to decode and reply to the packets. Hence the reason for the book.

pcie for dummies | Altera Community

12 Replies

Altera_Forum
Honored Contributor
9 years ago
I've only worked with PCIe on Arria 10 but I assume the PCIe hard IP core is set up the same on Cyclone V. The easiest way to generate interrupts is to use the legacy interrupt capability. The MSI stuff is complicated. To enable legacy interrupts go into the Avalon-MM settings tab for the PCIe core in Qsys and check the box for "Export MSI/MSI-X conduit interfaces". Doing that exposes some new ports on the PCIe block. The signals you're interested in are intx_req and intx_ack. To generate an interrupt you will assert the intx_req line. The core then asserts intx_ack when the interrupt packet has been sent to the root port (PC). Software (on the PC) also has to change a bit in a register in the endpoint configuration space to enable the legacy interrupt generation. If intx_ack is not asserted after you assert intx_req then you don't have interrupts enabled. You can read about all of this in the user guide for the PCIe hard IP block. Just search for "legacy interrupts" in the pdf.

I assume you have PCIe transfers working between the end point and PC and just need to get interrupts working. If you don't even have PCIe transfers working then you need to get technical help from Altera or someone else.
Altera_Forum
Honored Contributor
9 years ago
Hi rsefton. I'm not skill with pcie.
Can you explain me if i must use the avalonst or avalonmm examples?
And can you explain me if for my project is better
to use a internal memory example or a external sdram
example?
The idea is:
1) the board generates 64kB of data
2) the board send with dma 64kB to sdram of PC
3)the board checks if. Dma is complete (is possible?)
4)the board send interrupt to pc.
5)the pc read 64kB of data from pc sdram.
6) the pc executes a dma write to board for inform it to send another 64kB of data

Forum Discussion

pcie for dummies

12 Replies

Recent Discussions

Agilex 5 Power

Agilex 5 Sulfur Partial Write Issue on F2H ACE‑Lite I/F (256‑bit) with AXI Master of 128‑bit

Cyclone 10 LP's Extended Industrial parts

Quartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" required

Quartus Pro simulation libraries for Riviera Pro