I've only worked with PCIe on Arria 10 but I assume the PCIe hard IP core is set up the same on Cyclone V. The easiest way to generate interrupts is to use the legacy interrupt capability. The MSI stuff is complicated. To enable legacy interrupts go into the Avalon-MM settings tab for the PCIe core in Qsys and check the box for "Export MSI/MSI-X conduit interfaces". Doing that exposes some new ports on the PCIe block. The signals you're interested in are intx_req and intx_ack. To generate an interrupt you will assert the intx_req line. The core then asserts intx_ack when the interrupt packet has been sent to the root port (PC). Software (on the PC) also has to change a bit in a register in the endpoint configuration space to enable the legacy interrupt generation. If intx_ack is not asserted after you assert intx_req then you don't have interrupts enabled. You can read about all of this in the user guide for the PCIe hard IP block. Just search for "legacy interrupts" in the pdf.
I assume you have PCIe transfers working between the end point and PC and just need to get interrupts working. If you don't even have PCIe transfers working then you need to get technical help from Altera or someone else.