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RFett's avatar
RFett
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4 years ago

PCIe example program on Cyclone 10CX105YU484

Quartus 19.3 / Intel provides a sample design pcie_ed with a pcie IP connecting to a simple RAM. It runs properly on the Development Kit for Cyclone 10 with a 2 lane gen 2 configuration, 64 bit @ 125...
Harris's avatar
Harris
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4 years ago

Hi RFett,

From your description, it seems the difference is the Quartus design between Dev Kit and your own board? I suggest you check the difference of Address Map in the Qsys designs. Thanks.

BR/Harris