Forum Discussion

Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

PCIe Endpoint to PCIe EndPoint communication

Is it possible to communicate between two pcie endpoint Hard IPs in FPGA. Do somebody tried it?Any references? the idea is to interface a PCIe device(can be a rootport) to pcie endpoint(in fpga) th...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

[Matt]is it possible to connect these 2 IPs which are configured as ENDPoint, So that one PCie EP receive the data from a RP and other EP will transfer data to another RP.

[BCT]I believe this is doable, but you need to build a logic within the FPGA to transfer the data data from AVMM/AVST port of one Hard PCIe IP to another PCIe IP. this is a very rare application, I am sorry to said that we do not have this kind of reference design.

One more thing that I curious is if you want to use 2 PCIe IPs from the FPGA connect to one RP. How you going to design the FPGA board's PCIe slot? One PCIe IP connect through slot and another connect through PCIE cable? Please note that A10 PCIE does not support bifurcation, thus you can't have 2 PCIE slot share the same slot.

And yes to your last question. Bridge is use to interface 2 EP.