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Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

PCIe Endpoint to PCIe EndPoint communication

Is it possible to communicate between two pcie endpoint Hard IPs in FPGA. Do somebody tried it?Any references? the idea is to interface a PCIe device(can be a rootport) to pcie endpoint(in fpga) th...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Sir,

Yes any EP device can initiate transaction to other EP through a bridge.

But what I am confusing here is you mentioned the FPGA EP will act as a bridge. I don't think we can use the FPGA as a bridge.

So, in your application, you will still need a physical bridge that connecting the 2 EP.

  • Matt1's avatar
    Matt1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    BCT_Intel..thanks for the reply.

    its just a misunderstanding about the bridge that i mentioned in my query.sorry for that.

    In some intel fpga i found 2 Hard PCie IP.

    my question , is it possible to connect these 2 IPs which are configured as ENDPoint, So that one PCie EP receive the data from a RP and other EP will transfer data to another RP.

    Do u have some reference designs for this..

    you mentioned about bridge is the cutom design(eg: dual port Ram) which need to be interfaced with these 2 Endpoints .Correct me if I am wrong?