New Contributor
Frequent ContributorHi Kalpitha,
Thank you for reaching out.
Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.
I shall come back to you with findings.
Thank you for your patience.
Best Regards,
ZulsyafiqH_Intel
New ContributorHello ZulsyafiqH_Intel,
Thank you for responding. I want to add few more findings I did during these days.
I have an update on this issue.
I found out that it is better to create my user code as a new IP (Avalon Slave), add my IP to the platform designer and connect the Avalon master of Hard PCIe IP to the my slave.
I have attached the screenshots of the platform designer and I have uploaded my new updated VHDL code of the Avalon slave.
On the PC (computer #1,where the Cyclone 10gx development board is on PCI slot) I use the tool "RW Everything", to detect the PCIe and to read and write to the memory.
With the project that I have created," RW Everything" detects the PCI Hard IP I have instantiated in my project. But unfortunately, read or write is not triggering at address "800000000"(It is the start Base address of my slave)
In the Platform designer where I have connect my Slave, the address allocated is quite huge and I am unable to change the end address, Memory start and end is the problem or the User Slave I have written is not a right way of defining the Slave?
