New ContributorPCIe avalon-mm Slave on cyclone 10gx development kit.
Hello!
I started to work with the Cyclone 10gx development kit recently. I am interested in PCIe Hard IP . I have downloaded the example designs and I have compiled them and tested on a PC, which works fine.
I want to write my own Avalon_mm slave, where I do a simple decoding of address to blink the LED's on development kit board. Well my main task is to control some registers in the FPGA through PCIe interface, the read and write of few registers mostly, for the moment not any complicated image data streaming and all.
For this, I have instantiated PCIe hard IP , and configured the application interface to be Avalon_mm, brought out the avalon_mm slave bus to external. And I have connected my led_blinking slave to PCI hard IP core.
This code compiles without any errors.
I use 'RW Everything' tool on the PC to detect the PCIe and to dump memory.
My compiled design is tested with this tool. here I see the PCIe hard IP is detected my PC. But the 'BAR' is not assigned. BAR0 and BAR2 are enabled during configuration. But this is not detected. therefore I cannot read or write to and address.
When I look into the example design. in the hierarchy, I see mm_interconnect_0 component which is missing in my design.
Can you please help me figure out what other interface signals I have to connect to get mm_interconnect_0 component on my design?
If I connect an onchip memory IP as a slave instead of my slave. I see this mm_interconnect_0 in the hierarcy.
