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Altera_Forum's avatar
Altera_Forum
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12 years ago

PCI express Hard IP in Cyclone V Channel connections

Hello:

I would like to know which transceiver pairs can connect to the PCI express hard IP blocks in Cyclone V.

I am referring to page 1-5 of document CV-53001. They seem to imply that the hard IP can only connect to two specific pairs, but then go on to say that they can implement 4 lane PCI express and indeed do so in the reference design.

"The PCIe HIP blocks are located accross CH 1 and CH 2 of bank GXB_L0 and ch1 and ch2 of bank GXB_L2." In other words, two HIP blocks each connecting to two specific tranceiver pairs.

I would guess that the PCIe HIP block could connect to any of the channels within the groups they show on this page, but the document does not say that.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Check out page 4-8 in CV-53004. It seems to be clearer for x1, x2 and x4 configurations for which transceivers are used for each configuration. Double check this against the schematic of a PCIe dev board if you are still concerned.

    Pete