PCI Express HARD IP implementation using STRATIX IV FPGA

hii,

sorry to say but i didn't mean that i don't know to PRESS the SIMULATE BUTTON in modelsim. my problem is that i don't know the exact input values and their correct sequence to simulate it. i have already gone through the document "IP Compiler for PCI Express user guide" of altera. also i have reffered the "PCI Express High Performance Reference design" document of altera but in this they have used QSYS approach. but i want megawizard plug-in manager approach. so please give me a solution.

Design

hii,

sorry for my late reply.

and thanks for your reply.

now i am trying to update quartus to 12+ version.

thank you.

hii,

i would like to know that is it possible to disable some of the pins(input/output) of pcie hard ip of stratix iv of quartus ii software.

please help asap.

hii,

please anyone help me for the above mentioned problem(s).

What kind of pins are you trying to disable.

I presume you are building an endpoint, not a switch or hub, so yes, you can disable some of the lanes, you do not have to use it with all 8. Besides that, depending on how you build it in the Wizard, a few pins are optional. For error checking for example you can use the tx_err or the fancier ECRC. there is also The mask bits you can use but are not obliged to. For the interrupt mechanism you can use any of legacy, legacy + MSI, or legacy + MSI + MSI-X. Besides that I think you have to use it all.

Do you mean you are having too many pins to implement it in the FPGA? In that case perhaps your synthesis is not set-up right. When you build the Hard-IP you get the simulation version that has several pins that do not exist in the IP, like the pipemode version of the lanes. If you try to synthesize that you will get a huge number of extra pins. You have to synthesize the version intended for synthesis.

-G

HII,

Is there any reference design of IP Compiler for PCIe HARD IP Implementation using MegaWizard Plug-In Manager?? Because on altera's site they have given the high performance reference design using Qsys.

please reply ASAP.

thank you.