PCI Express HARD IP implementation using STRATIX IV FPGA

What kind of pins are you trying to disable.

I presume you are building an endpoint, not a switch or hub, so yes, you can disable some of the lanes, you do not have to use it with all 8. Besides that, depending on how you build it in the Wizard, a few pins are optional. For error checking for example you can use the tx_err or the fancier ECRC. there is also The mask bits you can use but are not obliged to. For the interrupt mechanism you can use any of legacy, legacy + MSI, or legacy + MSI + MSI-X. Besides that I think you have to use it all.

Do you mean you are having too many pins to implement it in the FPGA? In that case perhaps your synthesis is not set-up right. When you build the Hard-IP you get the simulation version that has several pins that do not exist in the IP, like the pipemode version of the lanes. If you try to synthesize that you will get a huge number of extra pins. You have to synthesize the version intended for synthesis.

-G