PCI Express HARD IP implementation using STRATIX IV FPGA

hii,

sorry to say but i didn't mean that i don't know to PRESS the SIMULATE BUTTON in modelsim. my problem is that i don't know the exact input values and their correct sequence to simulate it. i have already gone through the document "IP Compiler for PCI Express user guide" of altera. also i have reffered the "PCI Express High Performance Reference design" document of altera but in this they have used QSYS approach. but i want megawizard plug-in manager approach. so please give me a solution.

Design