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Your answers have been very comprehensive and advanced. I am probably way too inexperienced to be able to fully use your help.
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The best way to learn, is to ask how others do things. But then you have to try it too; even if you get the wrong answer, at least you are on the path to learning something new.
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Think I looked for a quick fix, i.e. someone took a look at the attached pictures and said that my design should work just fine, guess it is much more complex than that. I will give it a try, to investigate the requirements.
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Next time post schematic pages in PDF format. Looking at snapshots of diagrams on a crappy website that has pop-ups is a pain. No-one will help you.
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From PowerPlay Power Analyzer:
Core Dynamic Dissipation: 0.5 mW
Core Static Dissipation: 50 mW
That is sort of the only data I've managed to acquire.
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This analysis is incorrect. You need to implement a 'typical' design, run modelsim to obtain a value-change-dump (.vcd) file (I think thats the right name), and then run that through PowerPlay. Its a pretty memory intensive process when it comes to large devices, so what I've done in the past is to create a design with banks of toggle registers. I implement a design containing a number of these registers controlled by a generic, and then get power estimates for 10%, 20%, 30%, etc, and then extrapolate to 100%. This can then be considered your worst-case design power load.
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Looked over the Cyclone IV datasheet without any success here.
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Its design dependent, so you have to analyze it.
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I've used same LDO Regulator as used on Terasic's dev-kit. The datasheet gives an example where a load change of 1.4 A will give a diff of 2.2 % Voltage, with a 10 uF ceramic cap.
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An evaluation board is by definition for 'evaluation'. There is no guarantee that that board could supply power to the worst-case design you can come up with.
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I have 17 ceramic Caps. From Wikipedia ESR per cermaic cap is < 0.015.
17*0.015 = 0.255 Ohm.
How can I use this?
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You need to read the documents and references :)
The ESR of the bulk decoupling is important. The ESRs work in parallel, i.e., if the ESR of a single cap is 15milli-Ohms, and I have 3 of them, then their effective ESR is 5milliOhm. If you have a load step of 1A, then expect to see a supply drop of 5mV. The FPGA core voltage requirements need to consider this load step voltage change, and any voltage ripple from the power supply, eg., a switch-mode supply generally has a rippled voltage.
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Did you see the picture of the power supplies. Do you think it is necessary to have all those caps close to the FPGA?
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The high-frequency capacitors should be as close as possible to the power pins on the FPGA. For BGA devices, I use via-in-pad and place the capacitors on the back-side of the board right on the vias that lead to the BGA pins. However, my designs can implement load steps of 15A per FPGA, so are at the extreme end of the scale. You want to get them as close as possible to the power pins (between a power and ground pin if you can, or drop a via to the ground plane as close to the capacitor ground pad as possible).
The 10uF capacitors can be placed as close as is convenient to the FPGA.
Cheers,
Dave
Honored Contributor
