Honored Contributor
Honored ContributorFirst of all, sorry for a re-post here!
Your answers have been very comprehensive and advanced. I am probably way too inexperienced to be able to fully use your help. Think I looked for a quick fix, i.e. someone took a look at the attached pictures and said that my design should work just fine, guess it is much more complex than that. I will give it a try, to investigate the requirements. --- Quote Start --- What is the maximum current on VCCINT this design is expected to operate with? --- Quote End --- From PowerPlay Power Analyzer: Core Dynamic Dissipation: 0.5 mW Core Static Dissipation: 50 mW That is sort of the only data I've managed to acquire. --- Quote Start --- What is the required transient response for a load-step of that load current (the data sheet will have the supply minimum and maximum requirements)? --- Quote End --- Looked over the Cyclone IV datasheet without any success here. --- Quote Start --- Can your supply meet that requirement? --- Quote End --- I've used same LDO Regulator as used on Terasic's dev-kit. The datasheet gives an example where a load change of 1.4 A will give a diff of 2.2 % Voltage, with a 10 uF ceramic cap. --- Quote Start --- The load step response for the maximum current draw will be a dip in voltage that is determined by the equivalent series resistance of the capacitors you have selected. --- Quote End --- I have 17 ceramic Caps. From Wikipedia ESR per cermaic cap is < 0.015. 17*0.015 = 0.255 Ohm. How can I use this? Did you see the picture of the power supplies. Do you think it is necessary to have all those caps close to the FPGA? Regards, mr_embedded
