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Altera_Forum's avatar
Altera_Forum
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13 years ago

Pausing target processor and other problems

I have problems with Nios programming. I'm developing an audio voice recorder with DE2 board.

I use Quartus II Subscription Edition 9.0 and Nios II 9.0 EDS.

First I programmed the Quartus .sof file to the device, a dialog "Open Core Plus IP" appeared. I did not click Cancel, I just let the dialog be there, as it has been advised in earlier posts in this forum. Then launched Nios IDE which contains the project that I succesfully built. When I try to run the program as Nios Hardware, I get a message

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00.

Pausing target processor: not responding.

Resetting and trying again: FAILED.

Leaving target processor paused.

I have checked pin assignments and they're ok. Also unused pins are set "As input tri-stated." My Nios system has audio codec controller component (copied from Chu Pong P.'s book), SDRAM, buttons, switches, and a LCD controller. Also CPU and JTAG-UART, sysid and 50 MHz clock are included. Outside the Nios system I have put the ALTPLL megafunction and assigned its inputs and outputs to appropriate locations according to tutorials.

I tried the Hello World and it gave the same error message. Then I tried Hello World Small, it gave another error message which was something about missing debug core:

"The ptf file describing this project indicates that the target processor does

not contain a debug core. nios2-download requires a debug core to access the

target processor. Please use SOPC builder to add a debug core to your

processor and then try again (or use a different example design)."

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I added the debug core, but now also the Hello world small gives the same error message.

    using cable "usb-blaster [usb-0]", device 1, instance 0x00.

    pausing target processor: not responding.

    resetting and trying again: failed.

    leaving target processor paused.

    Then I made an own project using tut_sopc_introduction_vhdl.pdf .

    It gives the same error. I set the timing constraint fmax=50 mhz. Timing report tells me the actual time is 98.89 mhz.

    I connected the reset to toggle switch and tried to run the program, having the toggle switch in both positions. Again same error.

    I also tried another toggle switch, again the same error.

    The Quartus also tells me that i use time-limited megafunctions, although I'm using only CPU, JTAG-UART, Sysid, and two PIOs and on-chip memory.

    I didn't close the "open core plus ip" dialog.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    The problem was solved.

    I downloaded the .sof file to the board with reset switch in logic high position.

    The reset of the DE2 board is active low (see tutorial "Introduction to the Altera SOPC Builder Using VHDL Design"). We don't want the processor to reset, so we must keep the reset switch in high state.

    This solution has already been used by user sudattuladhar in this forum.