New Contributorhi
I have a design that can be compiled. but part of design not use any source. I check RTL viewer, the part exist. but in technology map, it isn't existed.
Is it about timing constrait problem?
thanks.
this problem is getting weird. I am closing this thread in this moment.
New Contributorthis problem is getting weird. I am closing this thread in this moment.
Super ContributorI'd like to give a general answer in case other forum users are reviewing the thread.
"Disappearing" logic is never caused by timing problems.
It's usually due to the fact that the synthesis tool removes any redundant logic. Redundant are all parts of your design that don't affect an output signal. Popular reasons are missing module connections, unconnected clock or module is inadvertently hold in reset.
Regards
Frank
