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FvM
Super Contributor
3 years agoI'd like to give a general answer in case other forum users are reviewing the thread.
"Disappearing" logic is never caused by timing problems.
It's usually due to the fact that the synthesis tool removes any redundant logic. Redundant are all parts of your design that don't affect an output signal. Popular reasons are missing module connections, unconnected clock or module is inadvertently hold in reset.
Regards
Frank