Parallel Flash Loader for MAX V

Hi sstrell

thanks for the suggestion. I managed to do it and compile the PFL megafunction for my MAX V design. Can you please suggest me how to write a SDC file to constrain the paths. i tried using the SDC file that i wrote for my FPGA, but that does not constrain my paths. I can see from the PFL user guide that i have to set some false paths for the asynchronous paths. Can you please suggest me how to do it. i am attaching my sdc file that i wrote for the FPGA design.