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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

P-tile Debug toolkit design changes

Hi there, I am using Intel Agilex-F series development which uses P-tile. I am trying to enable P-tile Debug took kit on the Intel reference design. I am referring to Section 7.2 of P-tile Debug too...
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ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Binu,

  1. Please make sure that you have turn on Enable PHY reconfiguration on the Top-Level Settings tab if you are using xcvr_reconfig. For further information, you may refer link below, Section 4.13. PHY Reconfiguration Interface, 4.13. PHY Reconfiguration Interface (intel.com)
  2. Please make sure that you have do the pin assignment and please connect all needed. You may refer to the example design under https://cdrdv2.intel.com/v1/dl/getContent/736492 . For further information, you may refer to our page, installer package, https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agf014.html
  3. For the PCIe, did you connect to the host ? are you reboot the host after programming the .sof ?

Best regards,

zying