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Altera_Forum's avatar
Altera_Forum
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15 years ago

overlapping of tSU/tH

Merry Christmas and happy new year to you all

I came across the datasheet of an DAC from AnalogDevices (the AD9122) and noted that this device's data interface tSU/tH overlap each other from the clock edge:

|----------------------| clk (at pin)

---- tSU (- 0.05 ns at pin)

------------- tH (+ 0.6ns at pin)

This is my first time to note overlap of tSU/tH.

In the context of devices, tSU/tH is meant at pins but eventually it is the internal registers that are meant.

The clk/data path delays from pins to internal registers account for a shift of register timing window (Altera calls it Micro...). Such that either tSU or tH or none could have negative value with respect to clk edge.

(+ve tSU being infront of edge, and of +ve tH behind edge and vice versa).

However, the width of timing window should not change since both tSU and tH are affected both by delays equally, so it is merely a shift without overlap and according to well known equations.

The question is how could anyone explain the overlap of these values.

Any answer appreciated.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Interestingly, just as I posted the thread I re-examined the issue and it turned out to be my mis-interpretation of definitions. It is quite easy to misunderstand when things are not the "norm".

    It is not physical overlap but an overlap by definition (man-made).

    I am used to imagine the timing window shifting but never draw arrows from clk edge to both edges of the window.

    If we draw arrows, then it looks overlpped whenever the window crosses past the clk edge.

    It is been helpful anyway.