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YanTian's avatar
YanTian
Icon for New Contributor rankNew Contributor
1 year ago

Over voltage on IO FPGA pins lead bank voltage rise

Dear All, I used Arria V GX in my design, with a LDO to supply 3.3v to FPGA_IO bank VCCIOx. Due to some reasons, I connected 2 input IO pins with 5v level. At first, there is no error. But after ...
Generic Io
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.