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Luckyguide's avatar
Luckyguide
Icon for New Contributor rankNew Contributor
1 year ago

Output Voltage Higher than Maximum Voltage of GPIO

Dear all, I have written a code that sends out a PWM signal with a duty cycle of 50% at 12.5 MHz. I am using the DE10-Lite board with the MAX 10 FPGA and Quartus 23.1.1 software on Windows 11. When ...
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Luckyguide's avatar
Luckyguide
Icon for New Contributor rankNew Contributor
1 year ago
I can try to lower the amps, but I can’t change the slew rate.

Yes, there is only 1 destination pin.

The system has not yet been made, i hope to drive a Linear CCD sensor but i’d first like to replicate the signals sent to the CCD by programming it and measuring it using the oscilloscope. I still have to add some other components to complete that. I’ll try to apply your suggestion of a series termination at the source, when I have further info then I’ll post it.

For now I’m trying to fix an issue as my laptop crashed after which somehow doesn’t allow me to upload code to the board anymore. In the meantime, I hope my question can be answered as to how the output voltage can even reach 4.7V if I only send a 1 or a 0 from my program. Theoretically it should then only be 0-3.3V maximum with perhaps a little overshoot?
Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
@Luckyguide wrote:
I can try to lower the amps,

I don't believe the current is particularly relevant.

@Luckyguide wrote:
but I can’t change the slew rate.

Yes, there is only 1 destination pin.

Ok

@Luckyguide wrote:
I hope my question can be answered as to how the output voltage can even reach 4.7V if I only send a 1 or a 0 from my program. Theoretically it should then only be 0-3.3V maximum with perhaps a little overshoot?

I have already answered this. If an unterminated transmission line is driven, then the reflected voltage will return and add to the source drive voltage. I recommend you look up about this. An example article:

https://wiki-power.com/en/%E4%BF%A1%E5%8F%B7%E5%AE%8C%E6%95%B4%E6%80%A7-%E5%A4%B1%E7%9C%9F/#reflection-at-resistive-loads

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    do you know trace transmission line impedance? Depends on width and layer stackup, you can e.g. use popular Saturn PCB toolkit for calculation.
    MAX10 LVTTL33 4mA IO standard has about 60 ohm typical output impedance, not far from lower range of expextable trace impedance. In any case you don't get much overshoot at the driving pin but larger overshoot at open trace end. Where do you measure the shown waveform?

    I'm not sure if measured 4.7 V is real, it might be also caused by unsuitable probing. It's no easy to measure correct waveforms of fast FPGA output signals with passive probes.

    I calculate maximal overshoot magnitude of 4.125 V at open trace end for 60 ohm pin impedance and 100 ohm trace ( 3.3*2*100/(60+100) ), but trace impedance is most likely lower.