Output voltage doesn't match settings

Thank you. You are right about magic, I suppose. The board hasn't any jumpers.

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The FPGA I/O constraints must be set to match the I/O voltage (VCCIO), it does not happen the other way around.

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Sorry, but I don't understand =(

altera.com/education/univ/materials/boards/de1/unv-de1-board.html?GSA_pos=1&WT.oss_r=1&WT.oss=de1

Reference Manual - db.tt/ptDzPht

User Guide - db.tt/YE9hEsDo

Shematic - altera.com/products/devkits/altera/documents/cy2_fpga_starter_board_schematic.pdf

And you are right - I don't know what to look for =(