Altera_ForumHonored Contributor14 years agoOutput Pins stuck at VCC? Code issue? I am looking to latch an enable signal only when my fpga is addressed correctly and recieves a specific code. But i am having issues getting this to work. Is my code correct? Here is my verilo...Show More
Recent DiscussionsRegarding Power-Up Sequence for Agilex 5Cyclone V SoC 5CSXC6 Series GXB Utilization and LimitationsHow to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?Agilex 3 PLL in Source Synchronous mode ?writing a word to cfm1 using on chip flash ip on max10