Honored Contributor
Honored ContributorWould you recommend a MOSFET or a BJT array? I wonder whats the largest array I can get in an IC. One of the goals of the circuit is it should be able to test a harness of upto 300 or so wires.
This is one of the reasons I'd prefer having a large array, but I'm not sure if they are available. A quick look at Newark and it seems MOSFET arrays are mostly just in Dual or Quad. For 300 wires, I'd end up needing 150 ICs. One solution to this problem is to forget 300 wires on a single board and instead have multiple boards. For instance, one board could be the "master board" and this can have the MCU and two Max V CPLDs. With a 144TQFP 5M240Z Max V, this board would be able to test 114 wires. This board require "only" 57 open drain ICs, if they have dual mosfet. And, in order to test more than 114 wires we can cascade more "daughter boards". A daughter board could contain just two Max V CPLDs, just like in the previous configuration minus the MCU. In essence, we'd have a cascaded shift register for both ends. Of course, the registers will need a SO pin so they can load bits on each clock cycle. What do you think of this approach? The advantage of this approach is, in some ways, less complexity and its also more cost effective. Most wiring harnesses don't have 300 wires! So why build a single large PCB when most of the harness are only going to require, suppose, 150 wires? I can't use a single massive BGA package because it's very hard to get it soldered locally, so we're sticking with 144TQFPs for now. Is it not possible to use the open drain outputs mentioned in the Max V Handbook? I read through it, but it seems the current is still limited by the IO pin. Plus I like the added benefit of protection for the CPLDs against damage when using buffers. EDIT: Just so I understand, you're suggesting that I should still drive the CPLD as we previously discussed i.e. use tri-state for outputs that are not active and 1 (or a 0) for the output that is. All lines should have a pull down (or pull up) resistor. All of this I understand - but how would the transistor connect to all this? Here's my attempt at understanding that part: The pull down resistor will be between the transistor's base and ground. When there nothing present on the line, the pull down resistor will have 0V on the base and the transistor will be OFF. When there is a 1 present on the line, the 3.3V will drop across the pull down resistor and the transistor will be on. We connect the harness' wire to the emitter of this transistor and its collector to Vcc. The wire's other end(s) are connected to to pins on the receiving end CPLD. Is this what you were suggesting? I apologize for so many questions! I'm just a bit lost on where to go with this.
