Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Output IO Buff is too large; DDR3

Hello, I downloaded and ran the altdq_dqs example from Altera literature webside. The example claimed these IO BUFFs could handle up to 333.333 MHz (3ns), but I found that their output B...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Are you sending a source-synchronous clock and doing timing analysis? The buffer delay time shouldn't matter(and 2.1 is actually very fast), as you'd never meet timing just sending data. DDR3 sends a clock alongside the data. Since the clock will have a similar 2.1ns output buffer delay, they "cancel out" and it's really the skew between the two interfaces you need to be concerned about.

For the record, building a DDR3 interface from the basic components is probably a pretty large undertaking.