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greenlantern01's avatar
greenlantern01
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Output HSMC pin via Ethernet port on DE10 Standard FPGA

Hello, I am currently working on a DE10 Standard FPGA along with a DC2390 Daughter Card. I want to get the ADC output from the daughter card (HSMC) and output it via the Ethernet port on the DE10. ...
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tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


When generating the Triple-Speed Ethernet IP Core IP with RGMII, the TSE IP Core already has ALTDDIO megafunctions inside. rgmii_in[3:0], rx_control, rgmii_out[3:0], and tx_control ports of the TSE IP Core are supposed to be mapped to I/O IBUF, thus additional ALTDDIO_IN megafuction shouldn't be inserted between I/O IBUF and the TSE IP Core.


Regards

Jingyang, Teh


greenlantern01's avatar
greenlantern01
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

I somehow managed to get that error solved.

The design is now finally ready. I was trying to figure ways to test it. Is it possible to test this design via eclipse. I saw tutorials for testing the design using eclipse if nios 2 processor is used. But couldn't find any which use HPS.

Also is it possible to debug the design using signaltap?

Can you suggest some ways?

Thanks