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Altera_Forum's avatar
Altera_Forum
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18 years ago

Output Enable Groups

What is the purpose of assigning an output enable group to my DDR2 DQ and DQS signals, and will Quartus do this automatically?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Does this VREF problematic mean that a cyclone III (ep3c120 for me) with 6 Vref group on bank 3/4 will not support a 32 bit DDR2 Controller when using this two banks only?

Each VREF group can have max 9 outputs/bidir, meaning that only 6*9=54 output are available on bank 3/4, which is not enough for the 72 pins necessary to the 32 bit DDR2 controller? What do you mean?

FLo