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Altera_Forum
Honored Contributor
Honored ContributorOSERDES using DDR
Can DDR be used with a SERDES Megafunction implementation? I am trying to implement a single channel of 4 pararlell bits at a 350MHz input into a SERDES, but the output (at least in simulation) is on...
Altera_ForumHonored Contributor
Honored ContributorWhich FPGA family are you referring to? Highest DDR clock frequency is around 400 MHz, correspending to 800 MHz data rate. Higher data rates up to 1600 Mbps are available with Stratix dedicated SERDES.
