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the transform is simply the SubBytes transform used in the AES cipher system, is it true that the fpga nature is suitable for implementing a design using lut so it take less resources, and if I made ASIC design the carnaugh map optimization would take less resources than lut.
Thanks
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In ASICs you can design your own logic at gate level.
FPGA fabric does not have user gates. Instead it provides luts (and flips) to realise logic.
your input to truth table is input to lut and the lut output is the truth table of your logic. It is equivalent in functionality.
Carnaugh mapping is not needed for fpga as the tool optimises the code. In ASICs I assume tools can do that as well.
Boolean algebra and carnaugh are traditional manual methods. Why wouldn't modern tools not be able to do that instead? Just like you don't need to get sine(x) for x = 1: n using pen and paper, you use a tool.
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