On my Altera Cyclone IV board I have 2 options. 1) Download code file from SPI memory to FPGA using Active serial (AS) mode. 2) Download .sof file from PC via SPI Bridge to FPGA using Passive serial (PS) mode.

In AS mode, you need 4 signals while in PS mode apparently only 2 signals.

Active Serial Mode (AS)

SPI Memory To FPGA

DATA0 --> DATA0

DCLK <-- DCLK

nCS <-- nCSO

ASDI <-- ASDO

Passive Serial Mode (PS)

SPI Bridge to FPGA

DATA0 --> DATA0

DCLK --> DCLK

GPIO -–X nCSO

GPIO X— ASDO

Now what happen if I connect permanently ASDO of Altera Cyclone IV to ASDI (GPIO) on SPI Bridge?