On Chip Memory Configuration and Altera Megafunction

Hi! I have a Cyclone V device that has 5,662,720 block memory bits.I have implemented 3 dual port RAMs that are 8 bits wide and 139520 deep.I figured that each RAM would amount to 109 M10K blocks, and I have tested the design in hardware and it seems to work.All three of these RAMs were inferred in code and no IP core was used.

I have a few questions though :

1) Why does the Altera Megafunction provide depth only in powers of 2 like 2048(2^11)... 32768(2^15) ... 65536(2^16)?

Is it only so that the memory can be fully addressed by a n-bit pointer?

2) Why doesn't it go beyond 65536? Especially when I can infer 3 dual port RAMs of 139520(not a power of 2) depth?

3) How to know what sort of memory has been inferred? M10K, M4K, M9K? The megafunction GUI allows you to specify but I think there's no such provision possible when you try to infer it in code.

By this point, the synthesis report shows that I am using 3,348,000/5,662,720 block memory bits (59 percent).

Now, I tried to infer 6 single port RAMs 1 bit wide & 69120 deep.The design doesn't synthesize and gives the following warning :

"cannot convert all sets of registers into ram megafunctions when creating nodes..."

i get the warning despite having auto ram replacement turned on(by default).

Strangely, when I try to infer the same amount of memory in a different configuration like 8 bits wide and 51840 deep, the design works.

Why is this so?

Which is a more efficient memory design? High depth or High Width?

Thank you!